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Start Your HBM/2.5D Design Today

SK hynix, Inc., Amkor Technology, eSilicon, Northwest Logic and Avery Design Systems have joined forces to offer a complete High Bandwidth Memory (HBM) supply chain solution. HBM is a JEDEC-defined standard that utilizes 2.5D technology to interconnect a SoC and a HBM memory stack. Many companies are already using HBM to create very high-bandwidth, low-power products.

Learn about the components required to build an HBM design from companies that are delivering and supporting customer HBM/2.5D designs now.

Webinar Recorded Tuesday March 29th, 2016

CSI-2 and DSI Demo (Northwest Logic Fidus/Inrevium FMC)


Northwest Logic’s CSI-2 Rx and DSI Host Controller Core MIPI demonstration with Inrevium FIDUS’s Meticom-based, dual-MIPI FMC Board running with a Xilinx Virtex-7 development board.

This demo descriptions as follows: A 13 megapixel Omnivision camera provides a MIPI output running 4 lanes of data at 1200 Mbit/s for each lane. This camera data then goes to the Fidus/Invrevium MIPI D-PHY card. This card uses a Meticom chip to translate the MIPI signal into FPGA compatible signals. The data from the Meticom chip then goes into the Virtex-7 located on the development board. The Virtex-7 FPGA uses Northwest Logic’s CSI-2 Rx Controller Core to convert the data back into pixels. These pixel are bayer processed, gamma and color corrected, frame buffered and output to the HDMI display.

Additionally, the Virtex-7 FPGA uses Northwest Logic’s DSI Host Controller as well to drive a color bar pattern through the Inrevium MIPI D-PHY card into a MIPI-compatible 10 inch display. This display has a 1920×1080 resolution. The MIPI signals from the DSI Host Controller core are running at 1000 Mbit/s on each of the 4 data lanes.

For more information on the Inrevium FMC MIPI D-PHY Card click here.

CSI-2 – HDMI Demo (Northwest Logic, Mixel)

Northwest Logic and Mixel have created a new CSI-HDMI demo that features the Omnivision 13850 camera outputing 4K video over 4 MIPI data lanes, each running at 1.2 Gbit/s. The video runs through cables to Mixel’s D-PHY Test Chip. The D-PHY Test Chip receives the MIPI video stream and sends it to a Xilinx Virtex-7 located on the Xilinx VC707 board. Northwest Logic’s CSI-2 Rx Controller Core in the Virtex-7 processes the MIPI Camera Serial Interface protocol and extracts the video pixels. These pixels are then Beyer processed, color and gamma corrected and sent via HDMI to the 1080P display.

CSI – DSI Demo (Xylon, Northwest Logic, Xilinx)

A comprehensive Xilinx MIPI video demonstration system developed by Xilinx and Xilinx Alliance Premier members Northwest Logic and Xylon.

Xilinx managed to implement surprisingly low cost MIPI Display Serial Interface (DSI) and Camera Serial Interface 2 (CSI-2) interfaces by combining the Series 7 I/Os with a simple external logic built by resistors. The supported Series 7 devices include: Artix, Kintex and Virtex FPGAs, as well as Zynq-7000 All Programmable SoC.

The demo captures 4K2K (3840 x 2160 @60 fps) video by a MIPI-compatible video camera, processes the video and displays it on the MIPI-compatible display with resolution 1920 x 1200 @60 fps (1200p).

CSI – DSI Demo (Northwest Logic, Meticom)

Demonstration of Northwest Logic’s CSI-2 Controller Core and DSI Controller Core with Meticom’s FPGA Bridge IC.

DSI Demo (Northwest Logic, Mixel)

Demonstration of Northwest Logic’s DSI Controller Core with Mixel’s D-PHY.

DSI Demo (Altima, Northwest Logic, Meticom)

Demonstration of Altima’s MIPI Demo System using Northwest Logic’s DSI Controller Core with Meticom’s FPGA Bridge IC.

CSI – DVI Demo (Northwest Logic, Moving Pixel)

Demonstration of Northwest Logic’s CSI-2 Controller Core with Moving Pixel’s D-PHY card.

CSI – DVI Demo (Northwest Logic, Mixel)

Demonstration of Northwest Logic’s CSI-2 Controller Core with Mixel’s D-PHY.


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